//********************************
//******* zhoudaoxi **************
//********************************
module	AU8_REGEN(
		reset,
		clk155m_sys,
		
		fp_ppfa_regen,
		
		pl_ais_force,
		ptr_itpre_st1,
		ptr_itpre_st2,
		ptr_itpre_st3,
		ptr_itpre_st4,
		ptr_itpre_st5,
		ptr_itpre_st6,
		ptr_itpre_st7,
		ptr_itpre_st8,
		waddr_pl_h_t1,
		waddr_pl_h_t2,
		waddr_pl_h_t3,
		waddr_pl_h_t4,
		waddr_pl_h_t5,
		waddr_pl_h_t6,
		waddr_pl_h_t7,
		waddr_pl_h_t8,
		pi_chan_y3,
		
		raddr_pl,
		rdata_pl,
		
		fp_to_pohp,
		j1_to_pohp,
		spe_to_pohp,
		data_to_pohp,

		hp_fifo_ovf_1,
		hp_fifo_ovf_2,
		hp_fifo_ovf_3,
		hp_fifo_ovf_4,
		ptr_regen_st,
		h1_pos_y1
		);
//*************************
input			reset;
input			clk155m_sys;

input			fp_ppfa_regen;

input			pl_ais_force;
input	[1:0]	ptr_itpre_st1;
input	[1:0]	ptr_itpre_st2;
input	[1:0]	ptr_itpre_st3;
input	[1:0]	ptr_itpre_st4;
input	[1:0]	ptr_itpre_st5;
input	[1:0]	ptr_itpre_st6;
input	[1:0]	ptr_itpre_st7;
input	[1:0]	ptr_itpre_st8;

input	[4:0]	waddr_pl_h_t1;
input	[4:0]	waddr_pl_h_t2;
input	[4:0]	waddr_pl_h_t3;
input	[4:0]	waddr_pl_h_t4;
input	[4:0]	waddr_pl_h_t5;
input	[4:0]	waddr_pl_h_t6;
input	[4:0]	waddr_pl_h_t7;
input	[4:0]	waddr_pl_h_t8;

input	[2:0]	pi_chan_y3;

output	[9:0]	raddr_pl;
input	[8:0]	rdata_pl;

output			fp_to_pohp;
output			j1_to_pohp;
output			spe_to_pohp;
output	[7:0]	data_to_pohp;
output			hp_fifo_ovf_1;
output			hp_fifo_ovf_2;
output			hp_fifo_ovf_3;
output			hp_fifo_ovf_4;
output	[2:0]	ptr_regen_st;
output			h1_pos_y1;

//****************************
parameter		PTR_MAX = 10'd782;
parameter       NORM = 3'b000;
parameter       AIS  = 3'b001;
parameter       NDF  = 3'b010;
parameter       INC  = 3'b011;
parameter       DEC  = 3'b100;

reg		[2:0]	cnt4_chan;
reg		[8:0]	cnt270_col;
reg		[3:0]	cnt9_row;
reg		[1:0]	cnt3_col;

reg				h1_pos,h2_pos;
reg				h1_n_pos,h2_n_pos;
reg				h31h32h33_pos;
reg				h33_nn1n2_pos;
reg				col2_en;
reg				hp_spe;

//****************************
reg				h1_pos_y1,h1_pos_y2,h1_pos_y3,h1_pos_y4,h1_pos_y5,h1_pos_y6;
reg				h2_pos_y1,h2_pos_y2,h2_pos_y3,h2_pos_y4,h2_pos_y5,h2_pos_y6;
reg				h1_n_pos_y1,h1_n_pos_y2,h1_n_pos_y3,h1_n_pos_y4,h1_n_pos_y5,h1_n_pos_y6;
reg				h2_n_pos_y1,h2_n_pos_y2,h2_n_pos_y3,h2_n_pos_y4,h2_n_pos_y5,h2_n_pos_y6;
reg		[1:0]	cnt3_col_y1,cnt3_col_y2,cnt3_col_y3;
reg		[2:0]	cnt4_chan_y1,cnt4_chan_y2,cnt4_chan_y3,cnt4_chan_y4,cnt4_chan_y5;

//****************************
reg				must_be_ais;
reg				old_p_neq_old_j1pos;
reg				inc_ok;
reg				dec_ok;
reg		[1:0]	old_ctinu_cnt_add1;
reg		[9:0]	old_p_vlue_add1;
reg		[9:0]	old_p_vlue_sub1;

wire	[2:0]	old_st_y2;
wire	[9:0]	old_p_vlue_y2;
wire	[1:0]	old_ctinu_cnt_y2;
wire	[9:0]	old_j1pos_y2;

reg		[2:0]	old_st_y3;
reg		[9:0]	old_p_vlue_y3;
reg		[1:0]	old_ctinu_cnt_y3;
reg		[9:0]	old_j1pos_y3;
reg		[2:0]	old_st;
reg		[9:0]	old_p_vlue;
reg		[1:0]	old_ctinu_cnt;
reg		[9:0]	old_j1pos;
reg		[2:0]	old_st_y5;
reg		[9:0]	old_p_vlue_y5;
reg		[1:0]	old_ctinu_cnt_y5;
reg		[9:0]	old_j1pos_y5;

reg		[1:0]	new_ctinu_cnt;
reg		[9:0]	new_p_vlue;
reg		[2:0]	new_st;
wire	[2:0]	ptr_regen_st;

reg		[1:0]	new_ctinu_cnt_y5;
reg		[9:0]	new_p_vlue_y5;
reg		[2:0]	new_st_y5;
reg		[24:0]	st_data_in;

reg		[8:0]	rdata_pl_y1;
reg		[2:0]	new_st_y6;
reg		[9:8]	new_p_vlue_y6;
reg		[2:0]	old_st_y6;
reg		[7:0]	old_p_vlue_y6;

//**************************
reg				hp_spe_tmp;
reg				spe_real_y3,spe_real_y4,spe_real_y5,spe_real_y6;

reg				col2_en_y1,col2_en_y2;
reg				hp_spe_y1,hp_spe_y2;
reg				h31h32h33_pos_y1,h31h32h33_pos_y2;
reg				h33_nn1n2_pos_y1,h33_nn1n2_pos_y2;

reg		[9:0]	j1_pos_1,j1_pos_2,j1_pos_3,j1_pos_4;
reg		[9:0]	j1_pos_5,j1_pos_6,j1_pos_7,j1_pos_8;
reg		[9:0]	j1_pos_1_y4,j1_pos_2_y4,j1_pos_3_y4,j1_pos_4_y4;
reg		[9:0]	j1_pos_5_y4,j1_pos_6_y4,j1_pos_7_y4,j1_pos_8_y4;
reg		[9:0]	j1_pos_1_y5,j1_pos_2_y5,j1_pos_3_y5,j1_pos_4_y5;
reg		[9:0]	j1_pos_5_y5,j1_pos_6_y5,j1_pos_7_y5,j1_pos_8_y5;
reg		[9:0]	new_j1pos;

//**************************
reg		[4:0]	raddr_pl_h_t1,raddr_pl_h_t2,raddr_pl_h_t3,raddr_pl_h_t4;
reg		[4:0]	raddr_pl_h_t5,raddr_pl_h_t6,raddr_pl_h_t7,raddr_pl_h_t8;

reg		[4:0]	raddr_pl_h;
wire	[9:0]	raddr_pl;

reg		[4:0]	waddr_pl_h_t1_y1,waddr_pl_h_t1_y2;
reg		[4:0]	waddr_pl_h_t2_y1,waddr_pl_h_t2_y2;
reg		[4:0]	waddr_pl_h_t3_y1,waddr_pl_h_t3_y2;
reg		[4:0]	waddr_pl_h_t4_y1,waddr_pl_h_t4_y2;
reg		[4:0]	waddr_pl_h_t5_y1,waddr_pl_h_t5_y2;
reg		[4:0]	waddr_pl_h_t6_y1,waddr_pl_h_t6_y2;
reg		[4:0]	waddr_pl_h_t7_y1,waddr_pl_h_t7_y2;
reg		[4:0]	waddr_pl_h_t8_y1,waddr_pl_h_t8_y2;

reg		[4:0]	waddr_pl_sync_0;
reg		[4:0]	waddr_pl_sync_1;
reg		[4:0]	waddr_pl_sync_2;
reg		[4:0]	waddr_pl_sync_3;
reg		[4:0]	waddr_pl_sync_4;
reg		[4:0]	waddr_pl_sync_5;
reg		[4:0]	waddr_pl_sync_6;
reg		[4:0]	waddr_pl_sync_7;

reg				i_req_1,i_req_2,i_req_3,i_req_4,i_req_5,i_req_6,i_req_7,i_req_8;
reg				d_req_1,d_req_2,d_req_3,d_req_4,d_req_5,d_req_6,d_req_7,d_req_8;
reg				hp_fifo_ovf_t1,hp_fifo_ovf_t1_y1;
reg				hp_fifo_ovf_t2,hp_fifo_ovf_t2_y1;
reg				hp_fifo_ovf_t3,hp_fifo_ovf_t3_y1;
reg				hp_fifo_ovf_t4,hp_fifo_ovf_t4_y1;
reg				hp_fifo_ovf_t5,hp_fifo_ovf_t5_y1;
reg				hp_fifo_ovf_t6,hp_fifo_ovf_t6_y1;
reg				hp_fifo_ovf_t7,hp_fifo_ovf_t7_y1;
reg				hp_fifo_ovf_t8,hp_fifo_ovf_t8_y1;
reg				hp_fifo_ovf_1,hp_fifo_ovf_2,hp_fifo_ovf_3,hp_fifo_ovf_4;
reg				hp_fifo_ovf_5,hp_fifo_ovf_6,hp_fifo_ovf_7,hp_fifo_ovf_8;

wire	[4:0]	sub_addr_t1_y1,sub_addr_t2_y1,sub_addr_t3_y1,sub_addr_t4_y1;
wire	[4:0]	sub_addr_t5_y1,sub_addr_t6_y1,sub_addr_t7_y1,sub_addr_t8_y1;

//wire			j1_pos_y2;
//wire			j1_pos_y3;
wire			j1_pos_y5;

//*************************
reg		[9:0]	ind_ptr;

reg				fp_ppfa_regen_y1;
reg				fp_ppfa_regen_y2;
reg				fp_ppfa_regen_y3;
reg				fp_ppfa_regen_y4;
reg				fp_ppfa_regen_y5;
reg				fp_ppfa_regen_y6;
reg				fp_to_pohp;
reg				j1_to_pohp;
reg		[7:0]	data_after_regen_p;
reg		[7:0]	data_to_pohp;
reg				spe_to_pohp;

//************************************************
//************************************************
//************************************************
//*************** Regen Timing ******************
always @(posedge clk155m_sys or posedge reset)
begin
 	if(reset == 1'b1)
 		cnt4_chan <= 0;
 	else if(fp_ppfa_regen == 1'b1)
 		cnt4_chan <= 1;
 	else
 		cnt4_chan <= cnt4_chan + 1;
end

always @(posedge clk155m_sys or posedge reset)
begin
 	if(reset == 1'b1)
 		cnt270_col <= 0;
 	else if(fp_ppfa_regen == 1'b1)
 		cnt270_col <= 0;
 	else if(cnt4_chan==7)
 		if(cnt270_col == 9'd269)
 			cnt270_col <= 0;
 		else
 			cnt270_col <= cnt270_col + 1;
end

always @(posedge clk155m_sys or posedge reset)
begin
 	if(reset == 1'b1)
		cnt9_row <= 0;
	else if(fp_ppfa_regen == 1'b1)
		cnt9_row <= 0;
	else if((cnt270_col==9'd269)&&(cnt4_chan==7))
		if(cnt9_row == 4'd8)
			cnt9_row <= 0;
		else
			cnt9_row <= cnt9_row + 1;
end

always @(posedge clk155m_sys or posedge reset)
begin
 	if(reset == 1'b1)
		cnt3_col <= 0;
	else if(fp_ppfa_regen == 1'b1)
		cnt3_col <= 0;
	else if(cnt4_chan==7)
		if(cnt3_col == 2'd2)
			cnt3_col <= 0;
		else
			cnt3_col <= cnt3_col + 1;
end

always @(posedge clk155m_sys or posedge reset)
begin
 	if(reset == 1'b1)
		h1_pos <= 0;
	else if((cnt9_row==4'd2)&&(cnt270_col==9'd269)&&(cnt4_chan==7))
		h1_pos <= 1;
	else if((cnt9_row==4'd3)&&(cnt270_col==9'd0)&&(cnt4_chan==7))
		h1_pos <= 0;
end

always @(posedge clk155m_sys or posedge reset)
begin
 	if(reset == 1'b1)
		h1_n_pos <= 0;
	else if((cnt9_row==4'd3)&&(cnt270_col==9'd0)&&(cnt4_chan==7))
		h1_n_pos <= 1;
	else if((cnt9_row==4'd3)&&(cnt270_col==9'd2)&&(cnt4_chan==7))
		h1_n_pos <= 0;
end

always @(posedge clk155m_sys or posedge reset)
begin
 	if(reset == 1'b1)
		h2_pos <= 0;
	else if((cnt9_row==4'd3)&&(cnt270_col==9'd2)&&(cnt4_chan==7))
		h2_pos <= 1;
	else if((cnt9_row==4'd3)&&(cnt270_col==9'd3)&&(cnt4_chan==7))
		h2_pos <= 0;
end

always @(posedge clk155m_sys or posedge reset)
begin
 	if(reset == 1'b1)
		h2_n_pos <= 0;
	else if((cnt9_row==4'd3)&&(cnt270_col==9'd3)&&(cnt4_chan==7))
		h2_n_pos <= 1;
	else if((cnt9_row==4'd3)&&(cnt270_col==9'd5)&&(cnt4_chan==7))
		h2_n_pos <= 0;
end

always @(posedge clk155m_sys or posedge reset)
begin
 	if(reset == 1'b1)
		h31h32h33_pos <= 0;
	else if((cnt9_row==4'd3)&&((cnt270_col==9'd5)&&(cnt4_chan==7)))
		h31h32h33_pos <= 1;
	else if((cnt9_row==4'd3)&&((cnt270_col==9'd8)&&(cnt4_chan==7)))
		h31h32h33_pos <= 0;
end

always @(posedge clk155m_sys or posedge reset)
begin
 	if(reset == 1'b1)
		h33_nn1n2_pos <= 0;
	else if((cnt9_row==4'd3)&&((cnt270_col==9'd8)&&(cnt4_chan==7)))
		h33_nn1n2_pos <= 1;
	else if((cnt9_row==4'd3)&&((cnt270_col==9'd11)&&(cnt4_chan==7)))
		h33_nn1n2_pos <= 0;
end

always @(posedge clk155m_sys or posedge reset)
begin
 	if(reset == 1'b1)
		col2_en <= 0;
	else if(cnt4_chan==7)
		if(cnt3_col == 2'd1)
			col2_en <= 1;
		else if(cnt3_col == 2'd2)
			col2_en <= 0;
end

always @(posedge clk155m_sys or posedge reset)
begin
 	if(reset == 1'b1)
		hp_spe <= 1'b0;
	else if(cnt4_chan==7)
		if(cnt9_row==4'd3)
			begin
			if(cnt270_col==9'd5)
				hp_spe <= 1'b1;
			else if(cnt270_col==9'd269)
				hp_spe <= 1'b0;
			end
		else
			begin
			if(cnt270_col==9'd8)
				hp_spe <= 1'b1;
			else if(cnt270_col==9'd269)
				hp_spe <= 1'b0;
			end
end

//*************** Regen PTR *******************
always @(posedge clk155m_sys or posedge reset)
begin
	if(reset == 1'b1)
		begin
		h1_pos_y1 <= 0;
		h1_pos_y2 <= 0;
		h1_pos_y3 <= 0;
		h1_pos_y4 <= 0;
		h1_pos_y5 <= 0;
		h1_pos_y6 <= 0;
		h2_pos_y1 <= 0;
		h2_pos_y2 <= 0;
		h2_pos_y3 <= 0;
		h2_pos_y4 <= 0;
		h2_pos_y5 <= 0;
		h2_pos_y6 <= 0;
		h1_n_pos_y1 <= 0;
		h1_n_pos_y2 <= 0;
		h1_n_pos_y3 <= 0;
		h1_n_pos_y4 <= 0;
		h1_n_pos_y5 <= 0;
		h1_n_pos_y6 <= 0;
		
		h2_n_pos_y1 <= 0;
		h2_n_pos_y2 <= 0;
		h2_n_pos_y3 <= 0;
		h2_n_pos_y4 <= 0;
		h2_n_pos_y5 <= 0;
		h2_n_pos_y6 <= 0;
		cnt4_chan_y1 <= 0;
		cnt4_chan_y2 <= 0;
		cnt4_chan_y3 <= 0;
		cnt4_chan_y4 <= 0;
		cnt4_chan_y5 <= 0;
		end
	else
		begin
		h1_pos_y1 <= h1_pos;
		h1_pos_y2 <= h1_pos_y1;
		h1_pos_y3 <= h1_pos_y2;
		h1_pos_y4 <= h1_pos_y3;
		h1_pos_y5 <= h1_pos_y4;
		h1_pos_y6 <= h1_pos_y5;
		h2_pos_y1 <= h2_pos;
		h2_pos_y2 <= h2_pos_y1;
		h2_pos_y3 <= h2_pos_y2;
		h2_pos_y4 <= h2_pos_y3;
		h2_pos_y5 <= h2_pos_y4;
		h2_pos_y6 <= h2_pos_y5;
		h1_n_pos_y1 <= h1_n_pos;
		h1_n_pos_y2 <= h1_n_pos_y1;
		h1_n_pos_y3 <= h1_n_pos_y2;
		h1_n_pos_y4 <= h1_n_pos_y3;
		h1_n_pos_y5 <= h1_n_pos_y4;
		h1_n_pos_y6 <= h1_n_pos_y5;
		
		h2_n_pos_y1 <= h2_n_pos;
		h2_n_pos_y2 <= h2_n_pos_y1;
		h2_n_pos_y3 <= h2_n_pos_y2;
		h2_n_pos_y4 <= h2_n_pos_y3;
		h2_n_pos_y5 <= h2_n_pos_y4;
		h2_n_pos_y6 <= h2_n_pos_y5;
		
		cnt4_chan_y1 <= cnt4_chan;
		cnt4_chan_y2 <= cnt4_chan_y1;
		cnt4_chan_y3 <= cnt4_chan_y2;
		cnt4_chan_y4 <= cnt4_chan_y3;
		cnt4_chan_y5 <= cnt4_chan_y4;
		end
end


//*****************************************
//*****************************************
//*****************************************
always @(posedge clk155m_sys or posedge reset)
begin
	if(reset == 1'b1)
		must_be_ais <= 0;
	else
		case(cnt4_chan_y3)
			3'd0:must_be_ais <= (ptr_itpre_st1[0]|ptr_itpre_st1[1]);
			3'd1:must_be_ais <= (ptr_itpre_st2[0]|ptr_itpre_st2[1]);
			3'd2:must_be_ais <= (ptr_itpre_st3[0]|ptr_itpre_st3[1]);
			3'd3:must_be_ais <= (ptr_itpre_st4[0]|ptr_itpre_st4[1]);
			3'd4:must_be_ais <= (ptr_itpre_st5[0]|ptr_itpre_st5[1]);
			3'd5:must_be_ais <= (ptr_itpre_st6[0]|ptr_itpre_st6[1]);
			3'd6:must_be_ais <= (ptr_itpre_st7[0]|ptr_itpre_st7[1]);
			3'd7:must_be_ais <= (ptr_itpre_st8[0]|ptr_itpre_st8[1]);
		endcase
end

always @(posedge clk155m_sys or posedge reset)
begin
	if(reset == 1'b1)
		old_p_neq_old_j1pos <= 0;
	else if(old_p_vlue_y3 != old_j1pos_y3)
		old_p_neq_old_j1pos <= 1'b1;
	else
		old_p_neq_old_j1pos <= 0;
end

always @(posedge clk155m_sys or posedge reset)
begin
	if(reset == 1'b1)
		inc_ok <= 0;
	else if(old_ctinu_cnt_y3 >=2'd2)
		case(cnt4_chan_y3)
			3'd0:inc_ok <= i_req_1;
			3'd1:inc_ok <= i_req_2;
			3'd2:inc_ok <= i_req_3;
			3'd3:inc_ok <= i_req_4;
			3'd4:inc_ok <= i_req_5;
			3'd5:inc_ok <= i_req_6;
			3'd6:inc_ok <= i_req_7;
			3'd7:inc_ok <= i_req_8;
		endcase
	else
		inc_ok <= 0;
end

always @(posedge clk155m_sys or posedge reset)
begin
	if(reset == 1'b1)
		dec_ok <= 0;
	else if(old_ctinu_cnt_y3 >=2'd2)
		case(cnt4_chan_y3)
			3'd0:dec_ok <= d_req_1;
			3'd1:dec_ok <= d_req_2;
			3'd2:dec_ok <= d_req_3;
			3'd3:dec_ok <= d_req_4;
			3'd4:dec_ok <= d_req_5;
			3'd5:dec_ok <= d_req_6;
			3'd6:dec_ok <= d_req_7;
			3'd7:dec_ok <= d_req_8;
		endcase
	else
		dec_ok <= 0;
end

always @(posedge clk155m_sys or posedge reset)
begin
	if(reset == 1'b1)
		old_ctinu_cnt_add1 <= 0;
	else if(old_ctinu_cnt_y3 == 2'd2)
		old_ctinu_cnt_add1 <= 2;
	else
		old_ctinu_cnt_add1 <= old_ctinu_cnt_y3 + 1;
end

always @(posedge clk155m_sys or posedge reset)
begin
	if(reset == 1'b1)
		old_p_vlue_add1 <= 0;
	else if(old_p_vlue_y3 == PTR_MAX)
		old_p_vlue_add1 <= 0;
	else
		old_p_vlue_add1 <= old_p_vlue_y3 + 1;
end

always @(posedge clk155m_sys or posedge reset)
begin
	if(reset == 1'b1)
		old_p_vlue_sub1 <= 0;
	else if(old_p_vlue_y3 == 0)
		old_p_vlue_sub1 <= PTR_MAX;
	else
		old_p_vlue_sub1 <= old_p_vlue_y3 - 1;
end

always @ (must_be_ais or old_st or old_p_neq_old_j1pos or inc_ok or dec_ok or old_ctinu_cnt_add1
		or old_p_vlue_add1 or old_p_vlue_sub1 or old_p_vlue or old_j1pos)
begin
	case(old_st)
       	AIS:begin
            if(must_be_ais == 1'b1)
            	begin
                new_ctinu_cnt <= 0;
                new_p_vlue <= old_p_vlue;
                new_st <= AIS;
                end
			else 
                begin
                new_ctinu_cnt <= 0;
                new_p_vlue <= old_j1pos;
                new_st <= NDF;
                end
            end
        NDF:begin
        	casex({must_be_ais,old_p_neq_old_j1pos})
        	2'b1x:begin
            	new_ctinu_cnt <= 0;
            	new_p_vlue <= old_p_vlue;
            	new_st <= AIS;
            	end
            2'b01:begin
                new_ctinu_cnt <= 0;
            	new_p_vlue <= old_j1pos;
            	new_st <= NDF;
                end
            2'b00:begin
            	new_ctinu_cnt <= old_ctinu_cnt_add1;
            	new_p_vlue <= old_j1pos;
            	new_st <= NORM;
                end
            endcase
            end
		NORM:begin
			casex({must_be_ais,old_p_neq_old_j1pos,inc_ok,dec_ok})
			4'b1xxx:begin
            	new_ctinu_cnt <= 0;
            	new_p_vlue <= old_p_vlue;
				new_st <= AIS;
				end
			4'b01xx:begin
                new_ctinu_cnt <= 0;
            	new_p_vlue <= old_j1pos;
				new_st <= NDF;
                end
            4'b001x:begin
                new_ctinu_cnt <= 2'd2;
            	new_p_vlue <= old_p_vlue;
				new_st <= INC;
                end
            4'b0001:begin
                new_ctinu_cnt <= 2'd2;
            	new_p_vlue <= old_p_vlue;
				new_st <= DEC;
                end
            4'b0000:begin
            	new_ctinu_cnt <= old_ctinu_cnt_add1;
            	new_p_vlue <= old_p_vlue;
				new_st <= NORM;
                end
            endcase
            end

        INC:begin
            if(must_be_ais == 1'b1)
                begin
                new_ctinu_cnt <= 0;
            	new_p_vlue <= old_p_vlue;
                new_st <= AIS;
                end
            else
                begin
                new_ctinu_cnt <= 0;
                new_p_vlue <= old_p_vlue_add1;
                new_st <= NORM;
                end
            end
            
        DEC:begin
            if(must_be_ais == 1'b1)
                begin
                new_ctinu_cnt <= 0;
                new_p_vlue <= old_p_vlue;
                new_st <= AIS;
                end
            else
                begin
                new_ctinu_cnt <= 0;
                new_p_vlue <= old_p_vlue_sub1;
                new_st <= NORM;
                end
            end
           
        default:begin
        	new_ctinu_cnt <= 0;
        	new_p_vlue <= 0;
        	new_st <= NDF;
        	end
	endcase
end

always @ (*)
begin
	if(h1_pos_y5 == 1)
		st_data_in <= {new_st_y5,new_p_vlue_y5,new_ctinu_cnt_y5,old_j1pos_y5};
	else if(j1_pos_y5 == 1)
		st_data_in <= {old_st_y5,old_p_vlue_y5,old_ctinu_cnt_y5,new_j1pos};
	else
		st_data_in <= {old_st_y5,old_p_vlue_y5,old_ctinu_cnt_y5,old_j1pos_y5};
end


wire	[6:0]	null_st;
//AU8_REGEN_ST_RAM64x25 U_REGEN_ST_RAM64x25(
//	.clock			(clk155m_sys),
//	.wren			(h1_pos_y5|j1_pos_y5),
//	.wraddress		({5'd0,cnt4_chan_y5}),
//	.data			({7'd0,st_data_in}),

//	.rdaddress		({5'd0,cnt4_chan}),
//	.q				({null_st,old_st_y2,old_p_vlue_y2,old_ctinu_cnt_y2,old_j1pos_y2})
//	);

AU8_REGEN_ST_RAM64x25         U_REGEN_ST_RAM64x25(
   .clka                      ( clk155m_sys ),
   .wea                       ( h1_pos_y5|j1_pos_y5 ),
   .addra                     ( {5'd0,cnt4_chan_y5} ),
   .dina                      ( {7'd0,st_data_in} ),
   .clkb                      ( clk155m_sys ),
   .addrb                     ( {5'd0,cnt4_chan} ),
   .doutb                     ( {null_st,old_st_y2,old_p_vlue_y2,old_ctinu_cnt_y2,old_j1pos_y2} )
   );


always @(posedge clk155m_sys or posedge reset)
begin
	if(reset == 1'b1)
		begin
		old_st_y3 <= 0;
		old_p_vlue_y3 <= 0;
		old_ctinu_cnt_y3 <= 0;
		old_j1pos_y3 <= 0;
		
		old_st <= 0;
		old_p_vlue <= 0;
		old_ctinu_cnt <= 0;
		old_j1pos <= 0;
		
		old_st_y5 <= 0;
		old_p_vlue_y5 <= 0;
		old_ctinu_cnt_y5 <= 0;
		old_j1pos_y5 <= 0;
		
		new_ctinu_cnt_y5 <= 2'd0;
		new_p_vlue_y5 <= 10'd0;
		new_st_y5 <= 3'd0;
		end
	else
		begin
		old_st_y3 <= old_st_y2;
		old_p_vlue_y3 <= old_p_vlue_y2;
		old_ctinu_cnt_y3 <= old_ctinu_cnt_y2;
		old_j1pos_y3 <= old_j1pos_y2;
		
		old_st <= old_st_y3;
		old_p_vlue <= old_p_vlue_y3;
		old_ctinu_cnt <= old_ctinu_cnt_y3;
		old_j1pos <= old_j1pos_y3;
		
		old_st_y5 <= old_st;
		old_p_vlue_y5 <= old_p_vlue;
		old_ctinu_cnt_y5 <= old_ctinu_cnt;
		old_j1pos_y5 <= old_j1pos;
		
		new_ctinu_cnt_y5 <= new_ctinu_cnt;
		new_p_vlue_y5 <= new_p_vlue;
		new_st_y5 <= new_st;
		end
end

assign ptr_regen_st = old_st_y2;

//**************** Regen SPE *********************
always @(posedge clk155m_sys or posedge reset)
begin
	if(reset == 1'b1)
		begin
		col2_en_y1 <= 0;
		col2_en_y2 <= 0;
		hp_spe_y1 <= 0;
		hp_spe_y2 <= 0;
		h31h32h33_pos_y1 <= 0;
		h31h32h33_pos_y2 <= 0;
		h33_nn1n2_pos_y1 <= 0;
		h33_nn1n2_pos_y2 <= 0;
		spe_real_y3 <= 1'b0;
		spe_real_y4 <= 1'b0;
		spe_real_y5 <= 1'b0;
		spe_real_y6 <= 1'b0;
		cnt3_col_y1 <= 0;
		cnt3_col_y2 <= 0;
		cnt3_col_y3 <= 0;
		end
	else
		begin
		col2_en_y1 <= col2_en;
		col2_en_y2 <= col2_en_y1;
		hp_spe_y1 <= hp_spe;
		hp_spe_y2 <= hp_spe_y1;
		h31h32h33_pos_y1 <= h31h32h33_pos;
		h31h32h33_pos_y2 <= h31h32h33_pos_y1;
		h33_nn1n2_pos_y1 <= h33_nn1n2_pos;
		h33_nn1n2_pos_y2 <= h33_nn1n2_pos_y1;
		spe_real_y3 <= hp_spe_tmp;
		spe_real_y4 <= spe_real_y3;
		spe_real_y5 <= spe_real_y4;
		spe_real_y6 <= spe_real_y5;
		cnt3_col_y1 <= cnt3_col;
		cnt3_col_y2 <= cnt3_col_y1;
		cnt3_col_y3 <= cnt3_col_y2;
		end
end

always @(old_st_y2 or hp_spe_y2 or h31h32h33_pos_y2 or h33_nn1n2_pos_y2)
begin
	if(hp_spe_y2 == 1'b1)
		case(old_st_y2)
		INC:begin
			if(h31h32h33_pos_y2|h33_nn1n2_pos_y2)
				hp_spe_tmp <= 1'b0;
			else
				hp_spe_tmp <= 1'b1;
			end
		DEC:hp_spe_tmp <= 1'b1;
		default:begin
			if(h31h32h33_pos_y2)
				hp_spe_tmp <= 1'b0;
			else
				hp_spe_tmp <= 1'b1;
			end
		endcase
	else
		hp_spe_tmp <= 1'b0;
end

always @(posedge clk155m_sys or posedge reset)
begin
	if(reset == 1'b1)
		begin
		j1_pos_1 <= 0;
		j1_pos_2 <= 0;
		j1_pos_3 <= 0;
		j1_pos_4 <= 0;
		j1_pos_5 <= 0;
		j1_pos_6 <= 0;
		j1_pos_7 <= 0;
		j1_pos_8 <= 0;
		end
	else if(h2_pos_y2 == 1'b1)
		case(cnt4_chan_y2)
			3'd0:j1_pos_1 <= 0;
			3'd1:j1_pos_2 <= 0;
			3'd2:j1_pos_3 <= 0;
			3'd3:j1_pos_4 <= 0;
			3'd4:j1_pos_5 <= 0;
			3'd5:j1_pos_6 <= 0;
			3'd6:j1_pos_7 <= 0;
			3'd7:j1_pos_8 <= 0;
		endcase
	else if((hp_spe_y2==1'b1)&&(h31h32h33_pos_y2==1'b0)&&(col2_en_y2==1'b1))
		case(cnt4_chan_y2)
			3'd0:begin
				if(j1_pos_1 == PTR_MAX)
					j1_pos_1 <= 10'd0;
				else
					j1_pos_1 <= j1_pos_1 + 1;
				end
			3'd1:begin
				if(j1_pos_2 == PTR_MAX)
					j1_pos_2 <= 10'd0;
				else
					j1_pos_2 <= j1_pos_2 + 1;
				end
			3'd2:begin
				if(j1_pos_3 == PTR_MAX)
					j1_pos_3 <= 10'd0;
				else
					j1_pos_3 <= j1_pos_3 + 1;
				end
			3'd3:begin
				if(j1_pos_4 == PTR_MAX)
					j1_pos_4 <= 10'd0;
				else
					j1_pos_4 <= j1_pos_4 + 1;
				end
			3'd4:begin
				if(j1_pos_5 == PTR_MAX)
					j1_pos_5 <= 10'd0;
				else
					j1_pos_5 <= j1_pos_5 + 1;
				end
			3'd5:begin
				if(j1_pos_6 == PTR_MAX)
					j1_pos_6 <= 10'd0;
				else
					j1_pos_6 <= j1_pos_6 + 1;
				end
			3'd6:begin
				if(j1_pos_7 == PTR_MAX)
					j1_pos_7 <= 10'd0;
				else
					j1_pos_7 <= j1_pos_7 + 1;
				end
			3'd7:begin
				if(j1_pos_8 == PTR_MAX)
					j1_pos_8 <= 10'd0;
				else
					j1_pos_8 <= j1_pos_8 + 1;
				end
		endcase
end

always @(posedge clk155m_sys or posedge reset)
begin
	if(reset == 1'b1)
		begin
		j1_pos_1_y4 <= 10'd0;		j1_pos_2_y4 <= 10'd0;
		j1_pos_3_y4 <= 10'd0;		j1_pos_4_y4 <= 10'd0;
		j1_pos_5_y4 <= 10'd0;		j1_pos_6_y4 <= 10'd0;
		j1_pos_7_y4 <= 10'd0;		j1_pos_8_y4 <= 10'd0;
		j1_pos_1_y5 <= 10'd0;		j1_pos_2_y5 <= 10'd0;
		j1_pos_3_y5 <= 10'd0;		j1_pos_4_y5 <= 10'd0;
		j1_pos_5_y5 <= 10'd0;		j1_pos_6_y5 <= 10'd0;
		j1_pos_7_y5 <= 10'd0;		j1_pos_8_y5 <= 10'd0;
		end
	else
		begin
		j1_pos_1_y4 <= j1_pos_1;	j1_pos_2_y4 <= j1_pos_2;
		j1_pos_3_y4 <= j1_pos_3;	j1_pos_4_y4 <= j1_pos_4;
		j1_pos_5_y4 <= j1_pos_5;	j1_pos_6_y4 <= j1_pos_6;
		j1_pos_7_y4 <= j1_pos_7;	j1_pos_8_y4 <= j1_pos_8;
		j1_pos_1_y5 <= j1_pos_1_y4;	j1_pos_2_y5 <= j1_pos_2_y4;
		j1_pos_3_y5 <= j1_pos_3_y4;	j1_pos_4_y5 <= j1_pos_4_y4;
		j1_pos_5_y5 <= j1_pos_5_y4;	j1_pos_6_y5 <= j1_pos_6_y4;
		j1_pos_7_y5 <= j1_pos_7_y4;	j1_pos_8_y5 <= j1_pos_8_y4;
		end
end

always @(*)
begin
	if((rdata_pl[8]==1'b1)&&(spe_real_y5==1'b1))
		case(cnt4_chan_y5)
			3'd0:new_j1pos <= j1_pos_1_y5;
			3'd1:new_j1pos <= j1_pos_2_y5;
			3'd2:new_j1pos <= j1_pos_3_y5;
			3'd3:new_j1pos <= j1_pos_4_y5;
			3'd4:new_j1pos <= j1_pos_5_y5;
			3'd5:new_j1pos <= j1_pos_6_y5;
			3'd6:new_j1pos <= j1_pos_7_y5;
			3'd7:new_j1pos <= j1_pos_8_y5;
		endcase
	else
		new_j1pos <= 0;
end

assign j1_pos_y5 = rdata_pl[8]&spe_real_y5;

//*************************************
//*************************************
always @(posedge clk155m_sys or posedge reset)
begin
	if(reset == 1'b1)
		raddr_pl_h_t1 <= 0;
	else if(hp_fifo_ovf_1 == 1'b1)
		raddr_pl_h_t1 <= raddr_pl_h_t1 + 5'd16;
	else if((hp_spe_tmp==1'b1)&&(cnt4_chan_y2==0))
		if(cnt3_col_y2 == 2'd0)
			raddr_pl_h_t1 <= raddr_pl_h_t1 + 1;
		else
			raddr_pl_h_t1 <= raddr_pl_h_t1;
end

always @(posedge clk155m_sys or posedge reset)
begin
	if(reset == 1'b1)
		raddr_pl_h_t2 <= 0;
	else if(hp_fifo_ovf_2 == 1'b1)
		raddr_pl_h_t2 <= raddr_pl_h_t2 + 5'd16;
	else if((hp_spe_tmp==1'b1)&&(cnt4_chan_y2==1))
		if(cnt3_col_y2 == 2'd0)
			raddr_pl_h_t2 <= raddr_pl_h_t2 + 1;
		else
			raddr_pl_h_t2 <= raddr_pl_h_t2;
end

always @(posedge clk155m_sys or posedge reset)
begin
	if(reset == 1'b1)
		raddr_pl_h_t3 <= 0;
	else if(hp_fifo_ovf_3 == 1'b1)
		raddr_pl_h_t3 <= raddr_pl_h_t3 + 5'd16;
	else if((hp_spe_tmp==1'b1)&&(cnt4_chan_y2==2))
		if(cnt3_col_y2 == 2'd0)
			raddr_pl_h_t3 <= raddr_pl_h_t3 + 1;
		else
			raddr_pl_h_t3 <= raddr_pl_h_t3;
end

always @(posedge clk155m_sys or posedge reset)
begin
	if(reset == 1'b1)
		raddr_pl_h_t4 <= 0;
	else if(hp_fifo_ovf_4 == 1'b1)
		raddr_pl_h_t4 <= raddr_pl_h_t4 + 5'd16;
	else if((hp_spe_tmp==1'b1)&&(cnt4_chan_y2==3))
		if(cnt3_col_y2 == 2'd0)
			raddr_pl_h_t4 <= raddr_pl_h_t4 + 1;
		else
			raddr_pl_h_t4 <= raddr_pl_h_t4;
end

always @(posedge clk155m_sys or posedge reset)
begin
	if(reset == 1'b1)
		raddr_pl_h_t5 <= 0;
	else if(hp_fifo_ovf_5 == 1'b1)
		raddr_pl_h_t5 <= raddr_pl_h_t5 + 5'd16;
	else if((hp_spe_tmp==1'b1)&&(cnt4_chan_y2==4))
		if(cnt3_col_y2 == 2'd0)
			raddr_pl_h_t5 <= raddr_pl_h_t5 + 1;
		else
			raddr_pl_h_t5 <= raddr_pl_h_t5;
end

always @(posedge clk155m_sys or posedge reset)
begin
	if(reset == 1'b1)
		raddr_pl_h_t6 <= 0;
	else if(hp_fifo_ovf_6 == 1'b1)
		raddr_pl_h_t6 <= raddr_pl_h_t6 + 5'd16;
	else if((hp_spe_tmp==1'b1)&&(cnt4_chan_y2==5))
		if(cnt3_col_y2 == 2'd0)
			raddr_pl_h_t6 <= raddr_pl_h_t6 + 1;
		else
			raddr_pl_h_t6 <= raddr_pl_h_t6;
end

always @(posedge clk155m_sys or posedge reset)
begin
	if(reset == 1'b1)
		raddr_pl_h_t7 <= 0;
	else if(hp_fifo_ovf_7 == 1'b1)
		raddr_pl_h_t7 <= raddr_pl_h_t7 + 5'd16;
	else if((hp_spe_tmp==1'b1)&&(cnt4_chan_y2==6))
		if(cnt3_col_y2 == 2'd0)
			raddr_pl_h_t7 <= raddr_pl_h_t7 + 1;
		else
			raddr_pl_h_t7 <= raddr_pl_h_t7;
end

always @(posedge clk155m_sys or posedge reset)
begin
	if(reset == 1'b1)
		raddr_pl_h_t8 <= 0;
	else if(hp_fifo_ovf_8 == 1'b1)
		raddr_pl_h_t8 <= raddr_pl_h_t8 + 5'd16;
	else if((hp_spe_tmp==1'b1)&&(cnt4_chan_y2==7))
		if(cnt3_col_y2 == 2'd0)
			raddr_pl_h_t8 <= raddr_pl_h_t8 + 1;
		else
			raddr_pl_h_t8 <= raddr_pl_h_t8;
end

always @(*)
begin
	case(cnt4_chan_y3)
		3'd0:raddr_pl_h <= raddr_pl_h_t1;
		3'd1:raddr_pl_h <= raddr_pl_h_t2;
		3'd2:raddr_pl_h <= raddr_pl_h_t3;
		3'd3:raddr_pl_h <= raddr_pl_h_t4;
		3'd4:raddr_pl_h <= raddr_pl_h_t5;
		3'd5:raddr_pl_h <= raddr_pl_h_t6;
		3'd6:raddr_pl_h <= raddr_pl_h_t7;
		3'd7:raddr_pl_h <= raddr_pl_h_t8;
	endcase
end

assign raddr_pl = {cnt4_chan_y3,raddr_pl_h,cnt3_col_y3};

//*********** I_req and D_req ********************
always @(posedge clk155m_sys or posedge reset)
begin
	if(reset == 1'b1)
		begin
		waddr_pl_h_t1_y1 <= 0;
		waddr_pl_h_t1_y2 <= 0;
		waddr_pl_h_t2_y1 <= 0;
		waddr_pl_h_t2_y2 <= 0;
		waddr_pl_h_t3_y1 <= 0;
		waddr_pl_h_t3_y2 <= 0;
		waddr_pl_h_t4_y1 <= 0;
		waddr_pl_h_t4_y2 <= 0;
		waddr_pl_h_t5_y1 <= 0;
		waddr_pl_h_t5_y2 <= 0;
		waddr_pl_h_t6_y1 <= 0;
		waddr_pl_h_t6_y2 <= 0;
		waddr_pl_h_t7_y1 <= 0;
		waddr_pl_h_t7_y2 <= 0;
		waddr_pl_h_t8_y1 <= 0;
		waddr_pl_h_t8_y2 <= 0;
		end
	else
		begin
		waddr_pl_h_t1_y1 <= waddr_pl_h_t1;
		waddr_pl_h_t1_y2 <= waddr_pl_h_t1_y1;
		waddr_pl_h_t2_y1 <= waddr_pl_h_t2;
		waddr_pl_h_t2_y2 <= waddr_pl_h_t2_y1;
		waddr_pl_h_t3_y1 <= waddr_pl_h_t3;
		waddr_pl_h_t3_y2 <= waddr_pl_h_t3_y1;
		waddr_pl_h_t4_y1 <= waddr_pl_h_t4;
		waddr_pl_h_t4_y2 <= waddr_pl_h_t4_y1;
		waddr_pl_h_t5_y1 <= waddr_pl_h_t5;
		waddr_pl_h_t5_y2 <= waddr_pl_h_t5_y1;
		waddr_pl_h_t6_y1 <= waddr_pl_h_t6;
		waddr_pl_h_t6_y2 <= waddr_pl_h_t6_y1;
		waddr_pl_h_t7_y1 <= waddr_pl_h_t7;
		waddr_pl_h_t7_y2 <= waddr_pl_h_t7_y1;
		waddr_pl_h_t8_y1 <= waddr_pl_h_t8;
		waddr_pl_h_t8_y2 <= waddr_pl_h_t8_y1;
		end
end

always @(posedge clk155m_sys or posedge reset)
begin
	if(reset == 1'b1)
		begin
		waddr_pl_sync_0 <= 0;
		waddr_pl_sync_1 <= 0;
		waddr_pl_sync_2 <= 0;
		waddr_pl_sync_3 <= 0;
		waddr_pl_sync_4 <= 0;
		waddr_pl_sync_5 <= 0;
		waddr_pl_sync_6 <= 0;
		waddr_pl_sync_7 <= 0;
		end
	else
		begin
		if(waddr_pl_h_t1_y1==waddr_pl_h_t1_y2) begin waddr_pl_sync_0 <= waddr_pl_h_t1_y2; end
		if(waddr_pl_h_t2_y1==waddr_pl_h_t2_y2) begin waddr_pl_sync_1 <= waddr_pl_h_t2_y2; end
		if(waddr_pl_h_t3_y1==waddr_pl_h_t3_y2) begin waddr_pl_sync_2 <= waddr_pl_h_t3_y2; end
		if(waddr_pl_h_t4_y1==waddr_pl_h_t4_y2) begin waddr_pl_sync_3 <= waddr_pl_h_t4_y2; end
		if(waddr_pl_h_t5_y1==waddr_pl_h_t5_y2) begin waddr_pl_sync_4 <= waddr_pl_h_t5_y2; end
		if(waddr_pl_h_t6_y1==waddr_pl_h_t6_y2) begin waddr_pl_sync_5 <= waddr_pl_h_t6_y2; end
		if(waddr_pl_h_t7_y1==waddr_pl_h_t7_y2) begin waddr_pl_sync_6 <= waddr_pl_h_t7_y2; end
		if(waddr_pl_h_t8_y1==waddr_pl_h_t8_y2) begin waddr_pl_sync_7 <= waddr_pl_h_t8_y2; end
		end
end

assign sub_addr_t1_y1 = (waddr_pl_sync_0 - raddr_pl_h_t1);
assign sub_addr_t2_y1 = (waddr_pl_sync_1 - raddr_pl_h_t2);
assign sub_addr_t3_y1 = (waddr_pl_sync_2 - raddr_pl_h_t3);
assign sub_addr_t4_y1 = (waddr_pl_sync_3 - raddr_pl_h_t4);
assign sub_addr_t5_y1 = (waddr_pl_sync_4 - raddr_pl_h_t5);
assign sub_addr_t6_y1 = (waddr_pl_sync_5 - raddr_pl_h_t6);
assign sub_addr_t7_y1 = (waddr_pl_sync_6 - raddr_pl_h_t7);
assign sub_addr_t8_y1 = (waddr_pl_sync_7 - raddr_pl_h_t8);

//*******************
always @(sub_addr_t1_y1)
begin
	case(sub_addr_t1_y1)
		5'd3,5'd4,5'd5,5'd6,5'd7,5'd8,5'd9,5'd10:i_req_1 <= 1;
		default:i_req_1 <= 0;
	endcase
end

always @(sub_addr_t1_y1)
begin
	case(sub_addr_t1_y1)
		5'd22,5'd23,5'd24,5'd25,5'd26,5'd27,5'd28,5'd29:d_req_1 <= 1;
		default:d_req_1 <= 0;
	endcase
end

always @(sub_addr_t1_y1)
begin
	case(sub_addr_t1_y1)
		5'd0:hp_fifo_ovf_t1 <= 1;
		5'd1:hp_fifo_ovf_t1 <= 1;
		5'd2:hp_fifo_ovf_t1 <= 1;
		
		5'd29:hp_fifo_ovf_t1 <= 1;
		5'd30:hp_fifo_ovf_t1 <= 1;
		5'd31:hp_fifo_ovf_t1 <= 1;
		default:hp_fifo_ovf_t1 <= 0;
	endcase
end

//*********************
always @(sub_addr_t2_y1)
begin
	case(sub_addr_t2_y1)
		5'd3,5'd4,5'd5,5'd6,5'd7,5'd8,5'd9,5'd10:i_req_2 <= 1;
		default:i_req_2 <= 0;
	endcase
end

always @(sub_addr_t2_y1)
begin
	case(sub_addr_t2_y1)
		5'd22,5'd23,5'd24,5'd25,5'd26,5'd27,5'd28,5'd29:d_req_2 <= 1;
		default:d_req_2 <= 0;
	endcase
end

always @(sub_addr_t2_y1)
begin
	case(sub_addr_t2_y1)
		5'd0:hp_fifo_ovf_t2 <= 1;
		5'd1:hp_fifo_ovf_t2 <= 1;
		5'd2:hp_fifo_ovf_t2 <= 1;
		
		5'd29:hp_fifo_ovf_t2 <= 1;
		5'd30:hp_fifo_ovf_t2 <= 1;
		5'd31:hp_fifo_ovf_t2 <= 1;
		default:hp_fifo_ovf_t2 <= 0;
	endcase
end

//*********************
always @(sub_addr_t3_y1)
begin
	case(sub_addr_t3_y1)
		5'd3,5'd4,5'd5,5'd6,5'd7,5'd8,5'd9,5'd10:i_req_3 <= 1;
		default:i_req_3 <= 0;
	endcase
end

always @(sub_addr_t3_y1)
begin
	case(sub_addr_t3_y1)
		5'd22,5'd23,5'd24,5'd25,5'd26,5'd27,5'd28,5'd29:d_req_3 <= 1;
		default:d_req_3 <= 0;
	endcase
end

always @(sub_addr_t3_y1)
begin
	case(sub_addr_t3_y1)
		5'd0:hp_fifo_ovf_t3 <= 1;
		5'd1:hp_fifo_ovf_t3 <= 1;
		5'd2:hp_fifo_ovf_t3 <= 1;
		
		5'd29:hp_fifo_ovf_t3 <= 1;
		5'd30:hp_fifo_ovf_t3 <= 1;
		5'd31:hp_fifo_ovf_t3 <= 1;
		default:hp_fifo_ovf_t3 <= 0;
	endcase
end

//*********************
always @(sub_addr_t4_y1)
begin
	case(sub_addr_t4_y1)
		5'd3,5'd4,5'd5,5'd6,5'd7,5'd8,5'd9,5'd10:i_req_4 <= 1;
		default:i_req_4 <= 0;
	endcase
end

always @(sub_addr_t4_y1)
begin
	case(sub_addr_t4_y1)
		5'd22,5'd23,5'd24,5'd25,5'd26,5'd27,5'd28,5'd29:d_req_4 <= 1;
		default:d_req_4 <= 0;
	endcase
end

always @(sub_addr_t4_y1)
begin
	case(sub_addr_t4_y1)
		5'd0:hp_fifo_ovf_t4 <= 1;
		5'd1:hp_fifo_ovf_t4 <= 1;
		5'd2:hp_fifo_ovf_t4 <= 1;
		
		5'd29:hp_fifo_ovf_t4 <= 1;
		5'd30:hp_fifo_ovf_t4 <= 1;
		5'd31:hp_fifo_ovf_t4 <= 1;
		default:hp_fifo_ovf_t4 <= 0;
	endcase
end

//*******************
always @(sub_addr_t5_y1)
begin
	case(sub_addr_t5_y1)
		5'd3,5'd4,5'd5,5'd6,5'd7,5'd8,5'd9,5'd10:i_req_5 <= 1;
		default:i_req_5 <= 0;
	endcase
end

always @(sub_addr_t5_y1)
begin
	case(sub_addr_t5_y1)
		5'd22,5'd23,5'd24,5'd25,5'd26,5'd27,5'd28,5'd29:d_req_5 <= 1;
		default:d_req_5 <= 0;
	endcase
end

always @(sub_addr_t5_y1)
begin
	case(sub_addr_t5_y1)
		5'd0:hp_fifo_ovf_t5 <= 1;
		5'd1:hp_fifo_ovf_t5 <= 1;
		5'd2:hp_fifo_ovf_t5 <= 1;
		
		5'd29:hp_fifo_ovf_t5 <= 1;
		5'd30:hp_fifo_ovf_t5 <= 1;
		5'd31:hp_fifo_ovf_t5 <= 1;
		default:hp_fifo_ovf_t5 <= 0;
	endcase
end

//*******************
always @(sub_addr_t6_y1)
begin
	case(sub_addr_t6_y1)
		5'd3,5'd4,5'd5,5'd6,5'd7,5'd8,5'd9,5'd10:i_req_6 <= 1;
		default:i_req_6 <= 0;
	endcase
end

always @(sub_addr_t6_y1)
begin
	case(sub_addr_t6_y1)
		5'd22,5'd23,5'd24,5'd25,5'd26,5'd27,5'd28,5'd29:d_req_6 <= 1;
		default:d_req_6 <= 0;
	endcase
end

always @(sub_addr_t6_y1)
begin
	case(sub_addr_t6_y1)
		5'd0:hp_fifo_ovf_t6 <= 1;
		5'd1:hp_fifo_ovf_t6 <= 1;
		5'd2:hp_fifo_ovf_t6 <= 1;
		
		5'd29:hp_fifo_ovf_t6 <= 1;
		5'd30:hp_fifo_ovf_t6 <= 1;
		5'd31:hp_fifo_ovf_t6 <= 1;
		default:hp_fifo_ovf_t6 <= 0;
	endcase
end

//*******************
always @(sub_addr_t7_y1)
begin
	case(sub_addr_t7_y1)
		5'd3,5'd4,5'd5,5'd6,5'd7,5'd8,5'd9,5'd10:i_req_7 <= 1;
		default:i_req_7 <= 0;
	endcase
end

always @(sub_addr_t7_y1)
begin
	case(sub_addr_t7_y1)
		5'd22,5'd23,5'd24,5'd25,5'd26,5'd27,5'd28,5'd29:d_req_7 <= 1;
		default:d_req_7 <= 0;
	endcase
end

always @(sub_addr_t7_y1)
begin
	case(sub_addr_t7_y1)
		5'd0:hp_fifo_ovf_t7 <= 1;
		5'd1:hp_fifo_ovf_t7 <= 1;
		5'd2:hp_fifo_ovf_t7 <= 1;
		
		5'd29:hp_fifo_ovf_t7 <= 1;
		5'd30:hp_fifo_ovf_t7 <= 1;
		5'd31:hp_fifo_ovf_t7 <= 1;
		default:hp_fifo_ovf_t7 <= 0;
	endcase
end

//*******************
always @(sub_addr_t8_y1)
begin
	case(sub_addr_t8_y1)
		5'd3,5'd4,5'd5,5'd6,5'd7,5'd8,5'd9,5'd10:i_req_8 <= 1;
		default:i_req_8 <= 0;
	endcase
end

always @(sub_addr_t8_y1)
begin
	case(sub_addr_t8_y1)
		5'd22,5'd23,5'd24,5'd25,5'd26,5'd27,5'd28,5'd29:d_req_8 <= 1;
		default:d_req_8 <= 0;
	endcase
end

always @(sub_addr_t8_y1)
begin
	case(sub_addr_t8_y1)
		5'd0:hp_fifo_ovf_t8 <= 1;
		5'd1:hp_fifo_ovf_t8 <= 1;
		5'd2:hp_fifo_ovf_t8 <= 1;
		
		5'd29:hp_fifo_ovf_t8 <= 1;
		5'd30:hp_fifo_ovf_t8 <= 1;
		5'd31:hp_fifo_ovf_t8 <= 1;
		default:hp_fifo_ovf_t8 <= 0;
	endcase
end


//**************************
always @(posedge clk155m_sys or posedge reset)
begin
	if(reset == 1'b1)
		begin
		hp_fifo_ovf_t1_y1 <= 0;
		hp_fifo_ovf_t2_y1 <= 0;
		hp_fifo_ovf_t3_y1 <= 0;
		hp_fifo_ovf_t4_y1 <= 0;
		hp_fifo_ovf_t5_y1 <= 0;
		hp_fifo_ovf_t6_y1 <= 0;
		hp_fifo_ovf_t7_y1 <= 0;
		hp_fifo_ovf_t8_y1 <= 0;
		end
	else
		begin
		hp_fifo_ovf_t1_y1 <= hp_fifo_ovf_t1;
		hp_fifo_ovf_t2_y1 <= hp_fifo_ovf_t2;
		hp_fifo_ovf_t3_y1 <= hp_fifo_ovf_t3;
		hp_fifo_ovf_t4_y1 <= hp_fifo_ovf_t4;
		hp_fifo_ovf_t5_y1 <= hp_fifo_ovf_t5;
		hp_fifo_ovf_t6_y1 <= hp_fifo_ovf_t6;
		hp_fifo_ovf_t7_y1 <= hp_fifo_ovf_t7;
		hp_fifo_ovf_t8_y1 <= hp_fifo_ovf_t8;
		end
end

always @(posedge clk155m_sys or posedge reset)
begin
	if(reset == 1'b1)
		begin
		hp_fifo_ovf_1 <= 0;
		hp_fifo_ovf_2 <= 0;
		hp_fifo_ovf_3 <= 0;
		hp_fifo_ovf_4 <= 0;
		hp_fifo_ovf_5 <= 0;
		hp_fifo_ovf_6 <= 0;
		hp_fifo_ovf_7 <= 0;
		hp_fifo_ovf_8 <= 0;
		end
	else
		begin
		hp_fifo_ovf_1 <= (hp_fifo_ovf_t1&(~hp_fifo_ovf_t1_y1));
		hp_fifo_ovf_2 <= (hp_fifo_ovf_t2&(~hp_fifo_ovf_t2_y1));
		hp_fifo_ovf_3 <= (hp_fifo_ovf_t3&(~hp_fifo_ovf_t3_y1));
		hp_fifo_ovf_4 <= (hp_fifo_ovf_t4&(~hp_fifo_ovf_t4_y1));
		hp_fifo_ovf_5 <= (hp_fifo_ovf_t5&(~hp_fifo_ovf_t5_y1));
		hp_fifo_ovf_6 <= (hp_fifo_ovf_t6&(~hp_fifo_ovf_t6_y1));
		hp_fifo_ovf_7 <= (hp_fifo_ovf_t7&(~hp_fifo_ovf_t7_y1));
		hp_fifo_ovf_8 <= (hp_fifo_ovf_t8&(~hp_fifo_ovf_t8_y1));
		end
end




//**************** Regen FRAME *******************************
always @(posedge clk155m_sys or posedge reset)
begin
	if(reset == 1'b1)
		begin
		rdata_pl_y1 <= 0;
		new_st_y6 <= 0;
		new_p_vlue_y6 <= 0;
		old_st_y6 <= 0;
		old_p_vlue_y6 <= 0;
		fp_ppfa_regen_y1 <= 0;
		fp_ppfa_regen_y2 <= 0;
		fp_ppfa_regen_y3 <= 0;
		fp_ppfa_regen_y4 <= 0;
		fp_ppfa_regen_y5 <= 0;
		fp_ppfa_regen_y6 <= 0;
		end
	else
		begin
		rdata_pl_y1 <= rdata_pl;
		new_st_y6 <= new_st_y5;
		new_p_vlue_y6[9:8] <= new_p_vlue_y5[9:8];
		old_st_y6 <= old_st_y5;
		old_p_vlue_y6 <= old_p_vlue_y5[7:0];
		fp_ppfa_regen_y1 <= fp_ppfa_regen;
		fp_ppfa_regen_y2 <= fp_ppfa_regen_y1;
		fp_ppfa_regen_y3 <= fp_ppfa_regen_y2;
		fp_ppfa_regen_y4 <= fp_ppfa_regen_y3;
		fp_ppfa_regen_y5 <= fp_ppfa_regen_y4;
		fp_ppfa_regen_y6 <= fp_ppfa_regen_y5;
		end
end

always @ (new_st_y6 or new_p_vlue_y6)
begin
	case(new_st_y6)
		INC:ind_ptr[9:8] <= {~new_p_vlue_y6[9],new_p_vlue_y6[8]};
		DEC:ind_ptr[9:8] <= {new_p_vlue_y6[9],~new_p_vlue_y6[8]};
		default:ind_ptr[9:8] <= new_p_vlue_y6[9:8];
	endcase
end

always @ (old_st_y6 or old_p_vlue_y6)
begin
	case(old_st_y6)
		INC:ind_ptr[7:0] <= {~old_p_vlue_y6[7],old_p_vlue_y6[6],~old_p_vlue_y6[5],old_p_vlue_y6[4],~old_p_vlue_y6[3],old_p_vlue_y6[2],~old_p_vlue_y6[1],old_p_vlue_y6[0]};
		DEC:ind_ptr[7:0] <= {old_p_vlue_y6[7],~old_p_vlue_y6[6],old_p_vlue_y6[5],~old_p_vlue_y6[4],old_p_vlue_y6[3],~old_p_vlue_y6[2],old_p_vlue_y6[1],~old_p_vlue_y6[0]};
		default:ind_ptr[7:0] <= old_p_vlue_y6[7:0];
	endcase
end

always @ (pl_ais_force or spe_real_y6 or rdata_pl_y1 or h1_pos_y6 or h2_pos_y6 or old_st_y6 or new_st_y6 or ind_ptr)
begin
	casex({spe_real_y6,h1_pos_y6,h2_pos_y6})
	3'b1xx:begin
		if(pl_ais_force == 1)
			data_after_regen_p <= 8'hFF;
		else if(old_st_y6==AIS)
			data_after_regen_p <= 8'hFF;
		else
			data_after_regen_p <= rdata_pl_y1[7:0];
		end
	3'b01x:begin
		case(new_st_y6)
		NORM:data_after_regen_p <= {4'b0110,2'b10,ind_ptr[9:8]};
		AIS:data_after_regen_p <= {8'b1111_1111};
		NDF:data_after_regen_p <= {4'b1001,2'b10,ind_ptr[9:8]};
		INC:data_after_regen_p <= {4'b0110,2'b10,ind_ptr[9:8]};
		DEC:data_after_regen_p <= {4'b0110,2'b10,ind_ptr[9:8]};
		default:data_after_regen_p <= {8'b0110_1000};
		endcase
		end
	3'b001:begin
		case(old_st_y6)
		NORM:data_after_regen_p <= ind_ptr[7:0];
		AIS:data_after_regen_p <= 8'b1111_1111;
		NDF:data_after_regen_p <= ind_ptr[7:0];
		INC:data_after_regen_p <= ind_ptr[7:0];
		DEC:data_after_regen_p <= ind_ptr[7:0];
		default:data_after_regen_p <= ind_ptr[7:0];
		endcase
		end
	default:begin
			if(h1_n_pos_y6==1'b1)
				data_after_regen_p <= 8'h9B;
			else if(h2_n_pos_y6==1'b1)
				data_after_regen_p <= 8'hFF;
			else
				data_after_regen_p <= 8'h00;
			end
	endcase
end

always @(posedge clk155m_sys or posedge reset)
begin
	if(reset == 1'b1)
		fp_to_pohp <= 1'b0;
	else if(fp_ppfa_regen_y6 == 1'b1)
		fp_to_pohp <= 1'b1;
	else
		fp_to_pohp <= 1'b0;
end

always @(posedge clk155m_sys or posedge reset)
begin
	if(reset == 1'b1)
		j1_to_pohp <= 1'b0;
	else if((rdata_pl_y1[8]==1'b1)&&(spe_real_y6==1'b1))
		j1_to_pohp <= 1'b1;
	else
		j1_to_pohp <= 0;
end

always @(posedge clk155m_sys or posedge reset)
begin
	if(reset == 1'b1)
		begin
		spe_to_pohp <= 0;
		data_to_pohp <= 0;
		end
	else
		begin
		spe_to_pohp <= spe_real_y6;
		data_to_pohp <= data_after_regen_p;
		end
end


endmodule